1. Field of the Invention
The present invention generally relates to reduced power operation of digital circuitry and more specifically to a method and apparatus for operating logic circuitry with alternating power phases.
2. Description of the Related Art
Advances in VLSI fabrication in recent years have greatly increased the levels of integration in digital integrated circuitry with the advent of submicron geometries. However, there has also been an increase in the speed and functionality in such circuitry. One example is the Pentium III microprocessor, which has several million transistors in a 1 cm2 area. While these trends are good from the standpoint of delivering increased capabilities to the electronics consumer there has developed a major problem, which is the power consumption of these devices. The Pentium III processor, while having exceptional performance, also has exceptional power dissipationxe2x80x94in the range of about 27 watts for an 866 MHz Pentium III. Adding to the problem, many portable computer systems, such as laptops, personal organizers and cellular telephones, demand the use of the highest performance integrated circuitry but do not have the battery power to run such circuitry for extended periods of time. Battery systems simply have not kept pace with the demands of the technology. To make matters worse, many portable or mobile systems have physical size constraints that preclude the use of extensive cooling devices to remove the power from the integrated circuitry.
Most of the digital integrated circuitry used for today""s high performance and high power devices is CMOS circuitry. Power consumption for CMOS circuitry is the sum of static power dissipation and dynamic power dissipation. The former PS is the result of leakage current while the latter PD is the sum of transient power consumption PT and capacitive-load power consumption PL.
Transient power consumption PT, in turn, results from current that travels between the supply and ground (known as through current) when the CMOS device switches and current required to charge internal switching nodes within the device (known as switching current), the charging and discharging of internal nodes being the predominant cause. Capacitive-load power consumption PL is caused by charging and discharging an external load capacitance.
FIG. 1 shows a typical CMOS inverter circuit 10 which includes a p-channel 14 and an n-channel 16 MOS transistor, the gates of the transistors being connected together and to the inverter input 12, the drains of the transistors being connected together and to the inverter output 18. The source of the p-channel transistor is connected to the voltage supply 22 and the source of the n-channel transistor is connected to ground 24. The output of the inverter is connected to other CMOS circuitry whose loading characteristics are capacitive in nature. This external capacitive loading is modeled by a capacitor 20 connected to the inverter output 18. When the input 12 to the logic circuit is driven low, p-channel transistor 14 turns on, causing the capacitive load 18 with value CL to be charged from the supply 22 through the p-channel transistor 14 and registering a logic ONE at the output 18. Similarly, when the input 12 is driven high, the p-channel transistor 14 turns off and the n-channel transistor 16 turns on allowing charge stored in the capacitive load 20 to be transferred through the n-channel transistor 16 to ground 24, thus registering a logic ZERO at the output 18. Each cycle of the input signal results in a transfer of charge to and from the capacitive load 20, which is equivalent to an energy transfer of (xc2xd CLxcex94VC2) to charge and (xc2xd CLxcex94Vd2) to discharge the capacitive load, where CL is the value of the capacitive load, xcex94Vc is the change in voltage across the capacitive load when charging the load and xcex94Vd is change in voltage across the capacitive load when discharging the load. This energy xc2xdCL(xcex94Vc2+xcex94Vd2) is dissipated as heat. Ultimately, the dynamic energy, on the order of 10xe2x88x9212 Joules (assuming CL to be about 1 pf, which includes load and wiring capacitance, and xcex94V to be about a volt), used to operate the circuit of FIG. 1 over a single cycle is lost.
Furthermore, if the cycle of charging and discharging occurs at a frequency f then the power consumed by the circuit of FIG. 1 is approximately fC(xcex94V)2 where equal voltage changes are assumed for charging and discharging. Currently, the frequency of operation of CMOS circuits is as high as 109 Hz. This means that even though the energy consumed over one cycle by a simple CMOS gate is very low, the power consumed when a gate is operated continuously at very high frequencies can be appreciable (on the order of 10xe2x88x923 Watts). When there are millions of such gates on a semiconductor die the problem is again multiplied resulting in many tens of Watts being consumed and a large fraction of that power being dissipated as heat.
A common approach to alleviate this problem has been to reduce the supply voltage because the savings in power consumption is proportional to the square of the voltage reduction. However, reduction of the power supply voltage causes other problems which include increasing the susceptibility of the circuit to noise and increased transistor leakage current because the threshold voltage of the MOS transistors must be reduced to permit the devices to operate on the lower supply voltage.
Therefore, there is a need for high-speed, high-functionality integrated circuit devices that have very low power consumption without depending on low supply voltages to achieve the reduction in power consumption.
The present invention is directed towards such a need. An apparatus of the invention includes logic circuitry having an energy storage node, an input clock having a cycle with a first phase and a second phase and an output and at least logic input, where the logic circuitry operates during the first phase of the clock and uses energy from the energy storage node to determine the logic output based on the logic input. An energy storage device is connected to the logic circuitry to capture energy used by the logic circuitry during the first phase and to supply the captured energy to the energy storage node during the second phase. Initialization circuitry is connected to the energy storage node, the energy storage device and to a reset line, and is configured to initially store energy on the energy storage node of the logic circuitry and to discharge the energy storage device in response to an active reset signal on a reset line.
A method in accordance with the present invention includes the steps of storing energy on a node in the logic circuitry and discharging an energy storage device while an initialization signal is active and while the initialization signal is inactive, operating the logic circuitry using the stored energy during a first phase of a clock signal, where the logic circuitry determines a logic output based on at least one logic input. The energy stored during the operation of the logic circuitry is then captured in an energy storage device, typically an inductor, and the captured energy is then returned from the energy storage node to the logic circuitry node during a second phase of the clock signal.
An advantage of the present invention is that higher performance and greater functionality is available for portable devices.
Another advantage is that the need for special cooling equipment is avoided or reduced and yet another advantage is that the battery life of portable equipment is longer.